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Energy and Transient Power Minimization during Behavioral Synthesis

The low-power design is driven by various factors, such as increase in chip density and clock frequency due to technology advances, thermal considerations, environmental concerns, reliability, and battery life. In low-power design for battery driven portable applications, the reduction of peak power, peak power differential, cycle difference power, average power and energy are equally important. These are different forms of dynamic power dissipation of a CMOS circuit, which is predominant compared to static power dissipation for higher switching activity. The peak power, the cycle difference power, and the peak power differential drive the transient characteristic of a CMOS circuit. In this dissertation, we propose frameworks for the reduction of energy and transient power through datapath scheduling during behavioral synthesis. The parameters that can be varied to control power consumption are supply voltage, clock frequency, switching activity and capacitance. While varying these parameters, their interactions and trade-off are considered. The quadratic variation of power dissipation with the supply voltage is of specific importance. Several ILP and heuristic based scheduling schemes are developed assuming three modes of datapath operation: single supply voltage and single frequency (SVSF), multiple supply voltages and dynamic frequency clocking (MVDFC), and multiple supply voltages and multicycling (MVMC). A new metric called cycle power function (CPF) has been defined, which captures the transient power characteristics of a datapath circuit. Minimizing CPF using MVDFC or MVMC under resource constraints leads to simultaneous reduction of energy and transient power. The cycle differential power, a measure of cycle power fluctuation is modeled as either the absolute deviation from the mean cycle power or as the cycle-to-cycle power gradient. To reduce the overall power fluctuation of the datapath, the mean power gradient (MPG) is minimized through datapath scheduling. Experimental results for selected high-level synthesis benchmark circuits under different constraints indicate that the MVDFC is a better design alternative compared to either the MVMC or the SVSF schemes.

Three different VLSI chips are designed and implemented for image watermarking applications. The different chips designed are as follows: spatial domain invisible watermarking chip, spatial domain visible watermarking chip, and DCT domain invisible-visible watermarking chip. All of these chips can be easily incorporated in a JPEG encoder or a digital camera. The DCT domain chip is designed for low power applications using dual supply voltage and dual frequency approach. The proposed architecture has a three stage pipeline structure and also exploits parallelism to improve the overall performance. The supply voltage and operating frequencies are fixed in such a way that there is a throughput match between the low operating frequency modules and high operating frequency modules. Level converters are used to connect the modules operating at different supply voltages. It is estimated that there is five fold reductions in average power consumption of the chip due to its dual voltage and dual frequency mode operation.

Dissertation from UMI

Complete Dissertation from USF library (pdf document)