Test 3 Syllabus

CSCE 5330/4730: Digital CMOS VLSI Design

Instructor: Dr. Saraju P. Mohanty

NOTE:

· This is closed book, closed text examination.

· Calculators are NOT allowed in the examination.

1. Velocity Saturation
2. Mobility Degradation
3. Channel length modulation
4. Body effect
5. Subthreshold conduction
6. Junction leakage
7. Gate oxide tunneling leakage
8. Operating temperature effects
9. Device geometry effects
10. Inverter fabrication steps
11. Layout design rules