Test 2 Syllabus

CSCE 5610/4610: Computer Architecture

Instructor: Dr. Saraju P. Mohanty

NOTE: This is closed book/text examination.

1. Response time versus throughput as computer performance
2. Various ways to improve performance
3. CPI metric
4. MIPS metric
5. Computer evaluation benchmarks
6. Amdahl’s law
7. Cost metric
8. Power metric
9. Execution cycle of an instruction
10. Single-cycle MIPS processor design supporting a subset of instruction
11. Working of single-cycle processor
12. Multi-cycle MIPS processor design supporting a subset of instruction
13. Single-cycle, multi-cycle, and pipelining comparison
14. Pipelined MIPS processor construction
15. Hazards in pipelining processors
16. Remedy of hazards in pipelining
17. Pipelined processor performance with stalls
18. Pipelined processor performance with different branch schemes