Test 3 Syllabus

CSCE 6730: Advanced VLSI Systems

Instructor: Dr. Saraju P. Mohanty

NOTE: This is closed book/text examination. 

1. Low-power design: Key Principles
2. Voltage, Frequency and Power Trade-offs
3. Low Power Design : Static Reduction
4. Tunneling Gate Capacitance of a Transistor
5. Gate Leakage Components in NMOS/PMOS Transistors
6. Gate Leakage Components in an Inverter
7. Three Metrics for Tunneling Current in CMOS transistor
8. Effect of Process and Design Parameter Variation on Three Transistor-Level  Metrics for Tunneling Current
9. Gate Leakage Analysis in Logic Gates
10. Three Metrics for Tunneling Current in Logic Gates
11. Effect of Process and Design Parameter Variation on Three Logic-Level  Metrics for Tunneling Current
12. Estimation of Gate Leakage at logic-level
13. Techniques for Gate Leakage Reduction
14. Concept of dynamic frequency clocking (DFC)
15. Time/Resources constrained energy-reduction scheduling using heuristic algorithm
16. Cycle power profile function
17. Heuristic algorithm to minimize transient power
18. ILP based algorithm for peak power reduction