Test 3 Syllabus

CSCE 5730/4730: Digital CMOS VLSI Design

Instructor: Dr. Saraju P. Mohanty


NOTE: This is closed book/text examination. 

  1. Transistor resistor-voltage Characteristics
  2. Transistor C-V Characteristics : Gate Capacitance
  3. Transistor C-V Characteristics : Overlap Capacitance
  4. Transistor C-V Characteristics : Diffusion Capacitance
  5. Transistor C-V Characteristics : 5 Components of Capacitance
  6. Velocity saturation in short-channel MOS device
  7. Mobility degradation in short-channel MOS device
  8. Channel length modulation in short-channel MOS device
  9. Body effect in short-channel MOS device
  10. Subthreshold conduction in short-channel MOS device
  11. Junction leakage in short-channel MOS device
  12. Gate leakage (tunneling) in short-channel MOS device
  13. Effect of Operating temperature in short-channel MOS device
  14. Effect of Device geometry in short-channel MOS device
  15. Process variation in nanoscale CMOS circuits
  16. Interconnect Impact on Chip
  17. Impact of Interconnect Parasitics
  18. The Parallel Plate Model of Wire Capacitance
  19. Fringing Capacitance of Wire
  20. Crosstalk in Wires
  21. Wire Resistance
  22. The Lumped Model of Wire Resistance
  23. The Lumped RC-Model using The Elmore Delay
  24. The Elmore Delay: RC Chain
  25. Propagation and Contamination of combination logic
  26. Switch-level RC Delay Models
  27. Effective Resistance and Capacitance
  28. Hierarhical design
  29. Layout design rules
  30. Design verification