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Presentations -- 2012:

  1. ISVLSI 2012 Talk (Geostatistical-Inspired Metamodeling and Optimization of Nano-CMOS Circuits)
  2. ISVLSI 2012 Talk (Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor Design)
  3. ISVLSI 2012 Talk (Metamodel-Assisted Fast and Accurate Optimization of an OP-AMP for Biomedical Applications)
  4. ISVLSI 2012 Talk (RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework)
  5. ISVLSI 2012 Talk (An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies)
  6. ICCCNT 2012 Talk (Design and Modeling of a Continuous-Time Delta-Sigma Modulator for Biopotential Signal Acquisition: Simulink Vs Verilog-AMS Perspective)
  7. UNT Global Discovery Workshop 2012 Talk, 26th June 2012 (Ultra-Fast Design Exploration of Nanoscale Circuit Through Metamodeling)
  8. GLSVLSI 2012 Talk (Verilog-AMS-PAM: Verilog-AMS integrated with Parasitic-Aware Metamodels for Ultra-Fast and Layout-Accurate Mixed-Signal Design Exploration)
  9. GLSVLSI 2012 Talk (STEP: A Unified Design Methodology for Secure Test and IP Core Protection)
  10. GLSVLSI 2012 Presentation (Particle Swarm Optimization over Non-Polynomial Metamodels for Fast Process Variation Resilient Design of Nano-CMOS PLL)
  11. Invited Talk, Semiconductor Research Corportation (SRC), Texas Analog Center for Excellence (TxACE), 27th April 2012 (Ultra-Fast Design Exploration of Nanoscale Circuits through Metamodeling)
  12. ISQED 2012 Talk (Metamodel-Assisted Ultra-Fast Memetic Optimization of a PLL for WiMax and MMDS Applications)
  13. ISQED 2012 Talk (Process Variation Tolerant 9T SRAM Bit Cell Design)
  14. ISQED 2012 Talk (Ordinary Kriging Metamodel-Assisted Ant Colony Algorithm for Fast Analog Design Optimization)
  15. ISQED 2012 Talk (Low Complexity Cross Parity Codes for Multiple and Random Bit Error Correction)
  16. VLSID 2012 Talk (Fast-Accurate Non-Polynomial Metamodeling for nano-CMOS PLL Design Optimization)
  17. VLSID 2012 Talk (Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier)
    18.

Last updated on 01 Jan 2013 (Tuesday).
© Saraju P. Mohanty