Website of Prof. Saraju P. Mohanty

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Publications -- 2004:

S. P. Mohanty and N. Ranganathan, "A Framework for Energy and Transient Power Reduction during Behavioral Synthesis", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 12, No. 6, June 2004, pp. 562-572 (Nominated for VLSI Transactions Best Paper Award 2006).
S. P. Mohanty, N. Ranganathan, and R. K. Namballa, "VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design", in Proceedings of the 17th International Conference on VLSI Design (VLSID), pp.1063-1068, 2004 (blind review, 92 full papers accepted out of 330 submissions, acceptance rate - 27.8%) .
S. P. Mohanty, N. Ranganathan, and S. K. Chappidi, " ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis", in Proceedings of the 17th International Conference on VLSI Design (VLSID), pp.745-748, 2004 (blind review, 92 full papers and 46 short papers accepted out of 330 submissions, acceptance rate - 41.8%).
S. P. Mohanty, R. Kumara C., and S. Nayak , "FPGA Based Implementation of an Invisible-Robust Image Watermarking Encoder", in Lecture Notes in Computer Science (LNCS), International Conference on Information Technology 2004,Springer-Verlag, Vol. 3356, pp. 344-353, 2004 (blind review, 44 full papers accepted out of 200 submissions, acceptance rate - 22%).