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Publications -- 2012:
  1. O. Garitselov, S. P. Mohanty, and E. Kougianos, “A Comparative Study of Metamodels for Fast and Accurate Simulation of Nano-CMOS Circuits”, IEEE Transactions on Semiconductor Manufacturing (TSM), Vol. 25, No. 1, February 2012, pp. 26--36.
  2. S. P. Mohanty and E. Kougianos, “DOE-ILP Assisted Conjugate-Gradient Optimization of High-κ/Metal-Gate Nano-CMOS SRAM”, IET Computers & Digital Techniques (CDT), Vol. 6, No. 4, July 2012, pp. 240--248.
  3. S. P. Mohanty, E. Kougianos, and O. Okobiah, “Optimal Design of a Dual-Oxide Nano-CMOS Universal Level Converter for Multi-Vdd  SoCs”, Springer Analog Integrated Circuits and Signal Processing Journal, Vol. 72, No. 2, August 2012, pp. 451--467.
  4. S. P. Mohanty, J. Singh, E. Kougianos, and D. K. Pradhan, “Statistical DOE-ILP Based Power-Performance-Process (P3) Optimization of Nano-CMOS SRAM”, Elsevier The VLSI Integration Journal, Vol. 45, No. 1, January 2012, pp. 33--45.
  5. O. Garitselov, S. P. Mohanty, and E. Kougianos, “Accurate Polynomial Metamodeling-Based Ultra-Fast Bee Colony Optimization of a Nano-CMOS PLL”, Special Issue on Power, Parasitics, and Process-Variation (P3) Awareness in Mixed-Signal Design, ASP Journal of Low Power Electronics (JOLPE), Volume 8, Issue 3, June, 2012, pp. 317--328.
  6. L. Sun, J. Mathew, D. K. Pradhan, and S. P. Mohanty, “Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits”, Special Issue on Power, Parasitics, and Process-Variation (P3) Awareness in Mixed-Signal Design, ASP Journal of Low Power Electronics (JOLPE), Volume 8, Issue 3, June, 2012, pp. 261--269.
  7. S. P. Mohanty, “New Circuit and Architecture Level Solutions for Multidiscipline Systems", Editorial, ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 8, Issue 3, August 2012, pp. 14:1--14:2.
  8. S. P. Mohanty, “ Power, Parasitics, and Process-Variation (P3) Awareness in Mixed-Signal Design", Editorial, ASP Journal of Low-Power Electronics (JOLPE), Volume 8, Issue 3, June 2012, pp. 259--260.
  9. S. P. Mohanty, “ISWAR: An Imaging System with Watermarking and Attack Resilience”, arXiv Computer Science, arXiv:1205.4489, May 2012, 21-pages.
    ISWAR (Imaging System with Watermarking and Attack Resilience) - Page
  10. O. Okobiah, S. P. Mohanty, E. Kougianos, and O. Garitselov, “Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier”, in Proceedings of the 25th International Conference on VLSI Design (VLSID), pp. 310--315, 2012. (blind review, 71 papers accepted out of 223 submissions, acceptance rate -- 31.8%)
  11. O. Garitselov, S. P. Mohanty, and E. Kougianos, “Fast-Accurate Non-Polynomial Metamodeling for nano-CMOS PLL Design Optimization”, in Proceedings of the 25th International Conference on VLSI Design (VLSID), pp. 316--321, 2012. (blind review, 71 papers accepted out of 223 submissions, acceptance rate -- 31.8%)
  12. O. Okobiah, S. P. Mohanty, and E. Kougianos, "Ordinary Kriging Metamodel-Assisted Ant Colony Algorithm for Fast Analog Design Optimization", in Proceedings of the 13th International Symposium on Quality Electronic Design (ISQED), pp. 458--463, 2012. (blind review)
  13. O. Garitselov, S. P. Mohanty, E. Kougianos, and O. Okobiah, "Metamodel-Assisted Ultra-Fast Memetic Optimization of a PLL for WiMax and MMDS Applications", in Proceedings of the 13th International Symposium on Quality Electronic Design (ISQED), pp. 580--585, 2012. (blind review)
  14. G. Zheng, S. P. Mohanty, E. Kougianos, and O. Garitselov, “Verilog-AMS-PAM: Verilog-AMS integrated with Parasitic-Aware Metamodels for Ultra-Fast and Layout-Accurate Mixed-Signal Design Exploration”, in Proceedings of the 21st ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 351--356, 2012. (blind review, 23 full and 18 short papers accepted out of 144 submissions, acceptance rate -- 28.5%)
  15. G. Zheng, S. P. Mohanty, and E. Kougianos, “Metamodel-Assisted Fast and Accurate Optimization of an OP-AMP for Biomedical Applications”, in Proceedings of the 11th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 273--278, 2012. (blind review)
  16. O. Okobiah, S. P. Mohanty, and E. Kougianos, “Geostatistical-Inspired Metamodeling and Optimization of Nano-CMOS Circuits”, in Proceedings of the 11th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 326--331, 2012. (blind review).
  17. O. Garitselov, S. P. Mohanty, E. Kougianos, and G. Zheng, “Particle Swarm Optimization over Non-Polynomial Metamodels for Fast Process Variation Resilient Design of Nano-CMOS PLL”, in Proceedings of the 21st ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 255--258, 2012. (blind review, 23 full, 18 short, and 30 poster papers accepted out of 144 submissions, acceptance rate -- 49.3%)
  18. O. Okobiah,  S. P. Mohanty, E. Kougianos, O. Garitselov, and G. Zheng, “Stochastic Gradient Descent Optimization for Low Power Nanoscale CMOS Thermal Sensor Design”, in Proceedings of the 11th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 285--290, 2012. (blind review)
  19. S. P. Mohanty, E. Kougianos, O. Garitselov, and J. M. Molina, “Polynomial-Metamodel Assisted Fast Power Optimization of Nano-CMOS PLL Components”, in Proceedings of the Forum on specification and Design Languages (FDL), pp. 233--238, 2012.
  20. M. Poolakkaparambil, J. Mathew, A. M. Jabir, and S. P. Mohanty, “Low Complexity Cross Parity Codes for Multiple and Random Bit Error Correction”, in Proceedings of the 13th International Symposium on Quality Electronic Design (ISQED), pp. 57--62, 2012. (blind review)
  21. M. Poolakkaparambil, J. Mathew, A. M. Jabir, and S. P. Mohanty, “An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies”, in Proceedings of the 11th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 141--146, 2012. (blind review)
  22. G. K. Reddy, K. Jainwal, J. Singh, and S. P. Mohanty, “Process Variation Tolerant 9T SRAM Bitcell Design”, in Proceedings of the 13th International Symposium on Quality Electronic Design (ISQED), pp. 492--496, 2012. (blind review)
  23. P. Yeolekar, R. A. Shafik, J. Mathew, D. K. Pradhan, and S. P. Mohanty, “STEP: A Unified Design Methodology for Secure Test and IP Core Protection”, in Proceedings of the 21st ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 333--338, 2012. (blind review, 23 full and 18 short papers accepted out of 144 submissions, acceptance rate -- 28.5%)
  24. R. A. Shafik, B. M. Al-Hashimi, J. Mathew, D. K. Pradhan, and S. P. Mohanty, “RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework”, in Proceedings of the 11th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 189--194, 2012. (blind review)
  25. G. Zheng, S. P. Mohanty, and E. Kougianos, “Design and Modeling of a Continuous-Time Delta-Sigma Modulator for Biopotential Signal Acquisition: Simulink Vs Verilog-AMS Perspective”, in Proceedings of the 3rd International Conference on Computing, Communication and Networking Technologies (ICCCNT), pp. 1--6, 2012.

Last updated on 08 May 2013 (Thu).
© Saraju P. Mohanty