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Publications -- 2014:
  1. O. Okobiah, S. P. Mohanty, and E. Kougianos, “Fast Layout Optimization through Simple Kriging Metamodeling: A Sense Amplifier Case Study”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Volume 22, Issue 4, April 2014, pp. 932--937.
  2. S. P. Mohanty and E. Kougianos, “Incorporating Manufacturing Process Variation Awareness in Fast Design Optimization of Nanoscale CMOS VCOs”, IEEE Transactions on Semiconductor Manufacturing (TSM), Volume 27, Issue 1, February 2014, pp. 22--31.
  3. S. P. Mohanty and E. Kougianos, “Polynomial Metamodel Based Fast Optimization of Nano-CMOS Oscillator Circuits”, Springer Analog Integrated Circuits and Signal Processing Journal, Volume 79, Issue 3, June 2014, pp. 437--453.
  4. S. P. Mohanty, M. Gomathisankaran, and E. Kougianos, “Variability-Aware Architecture Level Optimization Techniques for Robust Nanoscale Chip Design”, Elsevier International Journal on Computers and Electrical Engineering (IJCEE), Volume 40, Issue 1, January 2014, pp. 168--193.
  5. O. Okobiah, S. P. Mohanty, and E. Kougianos, “Nano-CMOS Thermal Sensor Design Optimization for Efficient Temperature Measurement”, Elsevier The VLSI Integration Journal, Volume 47, Issue 2, March 2014, pp. 195--203.
  6. A. Khan, S. P. Mohanty, and E. Kougianos, “Statistical Process Variation Analysis of a Graphene FET based LC-VCO for WLAN Applications”, in Proceedings of the 15th International Symposium on Quality Electronic Design (ISQED), 2014, pp. 569--574. (blind review)
  7. D. Ghai, S. P. Mohanty, G. Thakral, and O. Okobiah, “Variability-Aware DG FinFET-based Current Mirrors”, in Proceedings of the 23rd ACM Great Lakes Symposium on VLSI (GLSVLSI), 2014, pp. 347--352. (blind review, 29 regular papers and 20 short papers accepted out of 179 submissions, acceptance rate - 27.4%)
  8. O. Okobiah, S. P. Mohanty, and E. Kougianos, “Kriging Bootstrapped Neural Network Training for Fast and Accurate Process Variation Analysis”, in Proceedings of the 15th International Symposium on Quality Electronic Design (ISQED), 2014, pp. 365--372. (blind review)
  9. D. Roy, P. Ghosal, and S. P. Mohanty, “FuzzRoute: A Method For Thermally Efficient Congestion Free Global Routing in 3D ICs”, in Proceedings of the 13th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014, pp. 71--76. (blind review, 56 regular papers accepted out of 164 submissions, acceptance rate - 34.1%)
  10. E. Agu, S. P. Mohanty, E. Kougianos and M. Gautam, “Simscape Based Design Flow for Memristor Based Programmable Oscillators”, in Proceedings of the 23rd ACM Great Lakes Symposium on VLSI (GLSVLSI), 2014, pp. 223--224. (blind review, 29 regular papers, 20 short papers, and 27 poster papers accepted out of 179 submissions, acceptance rate - 42.4%)
  11. T. S. Das, P. Ghosal, S. P. Mohanty, and E. Kougianos, “A Performance Enhancing Hybrid Locally Mesh Globally Star NoC Topology”, in Proceedings of the 23rd ACM Great Lakes Symposium on VLSI (GLSVLSI), 2014, pp. 69--70. (blind review, 29 regular papers, 20 short papers, and 27 poster papers accepted out of 179 submissions, acceptance rate - 42.4%)
  12. A. Bose, P. Ghosal, and S. P. Mohanty, “A Low Latency Scalable 3D NoC Using BFT Topology with Table Based Uniform Routing”, in Proceedings of the 13th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014, pp. 136--141. (blind review, 56 regular papers and 25 poster papers accepted out of 164 submissions, acceptance rate - 49.4%)
  13. S. Ghosh, P. Ghosal, N. Das, S. P. Mohanty, and O. Okobiah, “Data Correlation Aware Serial Encoding for Low Switching Power On-Chip Communication”, in Proceedings of the 13th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014, pp. 124--129. (blind review, 56 regular papers and 25 poster papers accepted out of 164 submissions, acceptance rate - 49.4%)
  14. O. Okobiah, S. P. Mohanty, and E. Kougianos, "Exploring Kriging for Fast and Accurate Design Optimization of Nanoscale Analog Circuits", in Proceedings of the 13th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014, pp. 244--247. (Ph.D. Forum)
  15. D. Ghosh, P. Ghosal, and S. P. Mohanty, "A Highly Parameterizable Simulator for Performance Analysis of NoC Architectures", in Proceedings of the 13th International Conference on Information Technology (ICIT), pp. 311--315, 2014. (blind review, 68 papers accepted out of 186 submissions, acceptance rate - 36.5%)
  16. O. Okobiah, S. P. Mohanty, and E. Kougianos, "Exploring Kriging for Fast and Accurate Design Optimization of Nanoscale Analog Circuits", Poster, IEEE Texas Workshop on Integrated System Exploration (TexasWISE), University of Texas at Austin, Texas, March 21, 2014.
  17. P. Ghosal and S. P. Mohanty, "Architectural and Layout Level Optimization of Performance Centric 3D Nanosystem Design", Poster, IEEE Texas Workshop on Integrated System Exploration (TexasWISE), University of Texas at Austin, Texas, March 21, 2014.

Last updated on 13 Jan 2015 (Tue).
© Saraju P. Mohanty