Test 3 Syllabus

CSCE 5730/4730: Digital CMOS VLSI Design

Instructor: Dr. Saraju P. Mohanty

NOTE: This is closed book/text examination. 

1. Transistor as a switch with resistor
   
2. Transistor C-V Characteristics : Gate Capacitance
3. Transistor C-V Characteristics : Overlap Capacitance
4. Transistor C-V Characteristics : Diffusion Capacitance
5. Transistor C-V Characteristics : 5 Components of Capacitance
6. Velocity saturation in short-channel MOS device
   
7. Mobility degradation in short-channel MOS device
8. Channel length modulation in short-channel MOS device
9. Body effect in short-channel MOS device
10. Subthreshold conduction in short-channel MOS device
11. Junction leakage in short-channel MOS device
12. Gate leakage (tunneling) in short-channel MOS device
13. Effect of Operating temperature in short-channel MOS device
14. Effect of Device geometry in short-channel MOS device
15. Interconnect Impact on Chip
16. Impact of Interconnect Parasitics
17. The Parallel Plate Model of Wire Capacitance
18. Fringing Capacitance of Wire
19. Crosstalk in Wires
20. Wire Resistance
21. The Lumped Model of Wire Resistance
22. The Lumped RC-Model using The Elmore Delay
23. The Elmore Delay: RC Chain
24. Propagation and Contamination of combination logic
25. Switch-level RC Delay Models
26. Effective Resistance and Capacitance
27. Hierarchical Design through Design Partitioning
28. Hardware Description Language Modeling
29. Physical Design
30. Layout Design Rules