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Research Focus

The Smart Electronic Systems Laboratory (SESL) conducts research in Smart Electronics for the efficient realization of Internet-of-Things (IoT) based components for Smart Cities. The key aspects of the smart electronics are envisioned to be Energy-Smart, Security-Smart, and Response-Smart. Energy-Smart ensures that energy consumption of consumer electronics is minimal for longer battery life. Security-Smart deals with the security/protection of electronics systems as well as that of the information/media that these systems capture, process, or store. Response-Smart refers to accurate sensing, intelligent processing, and fast actuation/response. Smart Electronics in the framework of IoT can provide 3Is (Instrumentation, Interconnection, and Intelligence) to the Smart Cities. Optimal combinations of hardware and software modules are explored for ESR-smartness and design/operation cost trade-offs of electronic systems. The research of SESL can be classified into the following inter-related categories:

  1. Consumer Electronics for Smart Cities
  2. Energy-Efficiency and Security Methods for Internet-of-Things (IoT)
  3. Hardware and Software for Smart Healthcare
  4. Design and CAD for Digital, Mixed-Signal, Mixed-Discipline Systems
  5. VLSI Architecture for Multimedia Processing

Projects

  1. Memory Design Optimization for Low-Latency Embedded Vision Processor (LLEVS), Air Force STTR, NanoWatt Design, Inc., 2015-2016, Total Amount - $150,000 (UNT - $45,000), Principal Investigator - Mohanty, co-PI - Kougianos.
  2. Exploring Emerging Technology based Energy Efficient IoT Sensors for Smart Cities, Building Energy Efficiency Higher & Advanced Network (BHAVAN) Fellowship Program, Indo-US Science and Technology Forum (IUSSTF), 2016, Total Amount - $25,000 (Estimated), Senior Personnel - Mohanty, Visiting Scholar – J. Singh, Indian Institute of Information Technology, Design & Manufacturing, Jabalpur, India.
  3. Power and Thermal Aware Design of Three Dimensional Integrated Circuits and Network-on-Chips, Raman Fellowships for Post Doctoral Research, University Grants Commission, India, 2013-2014, Total Amount - $50,000 (Estimated), Senior Personnel - Mohanty, Visiting Scholar – P. Ghosal, Indian Institute of Engineering Science and Technology, Shibpur, India.
  4. Introduction of Nanoelectronics Courses in Undergraduate Computer Science and Computer Engineering Curricula, National Science Foundation (NSF), Division of Undergraduate Education (DUE) - Course, Curriculum, and Laboratory Improvement (CCLI), 2010-2013, Total Amount - $180,000, Principal Investigator - Mohanty, co-PI - Kougianos.
  5. Infrastructure Acquisition for Statistical Power, Leakage, and Timing Modeling Towards Realization of Robust Complex Nanoelectronics Circuits, National Science Foundation (NSF), Computer and Network Systems (CNS) - Computing Research Infrastructure (CRI), 2009-2012, Total Amount - $269,265 (includes $20,000 UNT matching), Principal Investigator - Mohanty, co-PI - Kougianos.
  6. Fast PVT-Tolerant Physical Design of RF IC Components, Semiconductor Research Corporation (SRC), Global Research Collaboration (GRC), Texas Analog Center of Excellence (TxACE), 2009-2012, Total Amount - $134,140 (includes $29,140 UNT matching), Principal Investigator - Mohanty, co-PI - Kougianos.
  7. Process Variation Aware Synthesis of Nano-CMOS Circuits, Engineering and Physical Sciences Research Council (EPSRC), UK, 2009-2012, Total Amount - £285,394, Senior Personel - Mohanty, (Principal Investigator - Dhiraj K. Pradhan, University of Bristol, UK).
  8. International Symposium on Electronic System Design (ISED), National Science Foundation (NSF), Computing and Communication Foundations (CCF) - Computer Architecture, 2010-2011, Total Amount - $14,000 (includes $4,000 UNT matching), Principal Investigator - Mohanty.
  9. A Comprehensive Methodology for Early Power-Performance Estimation of Nano-CMOS Digital Systems, National Science Foundation (NSF), Computing and Communication Foundations (CCF) - Computing Processes and Artifacts (CPA), 2007-2010, Total Amount - $200,000, Principal Investigator - Mohanty, co-PI - Kougianos.
  10. Development of Efficient Methodologies and Tools for Analog, Mixed-Signal and RF IC Design, Cadence Design Systems, Inc., Total Amount - $24,000, 2004-2005, Principal Investigator - Kougianos.
  11. The SPICE Modernization Project, ACM/IEEE Design Automation Conference Fellowship, 2005-2006, Total Amount - $24,000, Principal Investigator - Kougianos.
  12. Nanoelectronics Unified Fault Modeling and Experimentation - From Devices to Systems, Research Infrastructure Support Initiative, University of North Texas, 2008-2009, Total Amount - $24,000, Principal Investigator - Mohanty, co-PI - Kougianos.
  13. Watermarking Algorithms for Real-Time Copyright Protection and Subtitling during Digital Video Broadcasting in Internet Protocol Television (IP-TV), Faculty Research Grant, University of North Texas, 2008-2009, Total Amount - $5,000, Principal Investigator - Mohanty.
  14. Secure Digital Camera (SDC) for Biometric Authentication, Junior Faculty Summer Research Fellowship, University North Texas, 2007, Total Amount - $5,000, Principal Investigator - Mohanty.
  15. VLSI Architecture and Implementation of a Digital Video Broadcasting Network Processor (VNP) with Digital Rights Management (DRM) Facility, Junior Faculty Summer Research Fellowship, University of North Texas, 2006, Total Amount - $5,000, Principal Investigator - Mohanty.
  16. Behavioral Tools and Methodologies for Nanotechnology Design Automation, University of North Texas, 2006-2007, Total Amount - $5,000, Principal Investigator - Kougianos.
  17. Stochastic Techniques for the Characterization of VLSI Interconnects, University of North Texas, 2006-2007, Total Amount - $5,000, Principal Investigator - Kougianos.
  18. A Low Power Smart VLSI Controller for Nano-Characterization in Atomic Force Microscope (AFM), Junior Faculty Summer Research Fellowship, University of North Texas, 2005, Total Amount - $5,000, Principal Investigator - Mohanty.
  19. Leakage Current Reduction in Nanometer VLSI Circuits using Dual Gate Dielectrics, Faculty Research Grant, University of North Texas, 2005-2006, Total Amount - $4,000, Principal Investigator - Mohanty.

Publications

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