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SRC Grant P-10883: Fast PVT-Tolerant Physical Design of RF IC Components


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Project Scope

Background: The uncontrollable statistical variability in device characteristics represents major challenges to scaling and integration for present and next generation nano-CMOS transistors and circuits. This in turn demands revolutionary changes in the way in which current and future integrated circuits and systems are designed. Strong links must be established between circuit design, system design and fundamental device technology to allow circuits and systems to accommodate this increasing variability. Its major sources are: process variation (P), supply voltage (V), and operating temperature (T) which may be due to the environment, through self-heating effects or a combination of the two. Unfortunately, process, voltage and temperature (PVT) variability makes it hard to achieve “safe” integrated circuit designs in nanoscale technology and also causes loss of yield. While some attempts have been made to address PVT variation issues in digital circuits, no attempts have been made to address these for mixed-signal, analog, and radio frequency (RF) integrated circuits (IC) due to the increased complexity of the designs. Thus, the research will immensely advance the state-of-the-art of RF-IC design methodology.

Description: To have a process-variation robust design accounting for parasitics, power, and temperature, we will investigate a new “PVT tolerant RF IC design flow”. In a standard RF IC design flow, multiple iterations between the front-end circuit design and back-end layout are required to achieve parasitic closure. Such a manual approach requires X number of iterations. The goal of the proposed design flow is to reduce the number of manual iterations to 1, by performing the X number of iterations on a parasitic parameterized netlist instead of the layout. The parasitic parameterized netlist refers to the netlist derived from the initial physical design and then parameterized for optimization in X automatic iterations. The final physical design is done using the parameters obtained from the netlist optimized for a worst case process variation. This constitutes 1 iteration. Hence, this novel flow reduces the X number of manual iterations required for parasitic closure, to 1 manual iteration. This flow ensures that the final physical design is not only resistant to parasitic effects, but also process-variation tolerant. Thus, the RF IC design cycle can be significantly reduced resulting in lost cost RF ICs while enhancing PVT tolerance of the RF ICs, which will improve the RF IC yield. We will analyze average and worst case variations for standard nano-CMOS RF IC components such as VCOs and LNAs including: (1) center frequency, (2) phase-noise, (3) linearity, (4) throughput, (5) dynamic power dissipation, (6) subthreshold leakage,  and (7) gate-oxide leakage. We will then investigate the use of conjugate gradient method, simulated annealing method, and Monte Carlo method for optimization of various physical parameters once the parameterized full-blown parasitic netlist of an RF IC is obtained. We recently performed conjugate gradient method based optimization of center frequency of a nano-CMOS VCO.

Primary Anticipated Result: Novel design and optimization methodologies (not design) that can produce PVT-tolerant RFICs in one design iteration only and with minimal (at most two) manual layout steps to improve circuit yield (by accounting for process variation effects right at the design stage) and reduce chip cost.


Project Personnel

    Faculty:

  • Saraju P. Mohanty (Principal Investigator) -- Contributions to the Project include: Co-ordinating the overall project, generating new ideas and themes for publication, writing the research outcomes as papers, and making conference presentations.
  • Elias Kougianos (Co-Principal Investigator) -- Contributions to the Project include: Generating new ideas and themes for publication, training students on tools, and writing the research outcomes as papers.

    Students: The contributions include -- Implementing the ideas, generating the results, compiling results for publication, and making conference presentations.

  • Oleg Garitselov: Ph.D.(Computer Science and Engineering), Dissertation: "Metamodeling-Based Fast Optimization of Nanoscale AMS-SoC", Department of Computer Science and Engineering, University of North Texas, Spring 2012, major professor - Mohanty, co-major - Kougianos.
  • Garima Thakral: Ph. D. (Computer Science and Engineering), Dissertation: “Process-Voltage-Temperature Aware Nanoscale Circuit Optimization”, Department of Computer Science and Engineering, University of North Texas, Fall 2010, major professor - Mohanty, co-major - Kougianos. (First UNT woman Computer Science and Engineering Ph.D. with VLSI specialization.) (First Employment: Aperia Solutions)

Project Publications

  1. O. Garitselov, S. P. Mohanty, and E. Kougianos, “A Comparative Study of Metamodels for Fast and Accurate Simulation of Nano-CMOS Circuits”, IEEE Transactions on Semiconductor Manufacturing (TSM), Vol. 25, No. 1, February 2012, pp. 26--36.
  2. O. Garitselov, S. P. Mohanty, E. Kougianos, and O. Okobiah, "Metamodel-Assisted Ultra-Fast Memetic Optimization of a PLL for WiMax and MMDS Applications", in Proceedings of the 13th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 580--585, 2012 (blind review).
  3. O. Okobiah, S. P. Mohanty, and E. Kougianos, "Ordinary Kriging Metamodel-Assisted Ant Colony Algorithm for Fast Analog Design Optimization", in Proceedings of the 13th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 458--463, 2012 (blind review).
  4. O. Garitselov, S. P. Mohanty, and E. Kougianos, “Fast-Accurate Non-Polynomial Metamodeling for nano-CMOS PLL Design Optimization”, in Proceedings of the 25th IEEE International Conference on VLSI Design (VLSID), pp. 316--321, 2012 (blind review, 71 papers accepted out of 223 submissions, acceptance rate -- 31.8%).
  5. O. Okobiah, S. P. Mohanty, E. Kougianos, and O. Garitselov, “Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier”, in Proceedings of the 25th IEEE International Conference on VLSI Design (VLSID), pp. 310--315, 2012 (blind review, 71 papers accepted out of 223 submissions, acceptance rate -- 31.8%).
  6. S. P. Mohanty and E. Kougianos, “PVT-Tolerant 7-Transistor SRAM Optimization via Polynomial Regression”, in Proceedings of the 2nd IEEE International Symposium on Electronic System Design (ISED), pp. 39--44, 2011 (blind review, 62 papers accepted out of 146 submissions, acceptance rate – 42.4%).
  7. O. Garitselov, S. P. Mohanty, E. Kougianos, and P. Patra, “Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL”, in Proceedings of the 2nd IEEE International Symposium on Electronic System Design (ISED), pp. 6--11, 2011 (blind review, 62 papers accepted out of 146 submissions, acceptance rate – 42.4%).
  8. O. Garitselov, S. P. Mohanty, and E. Kougianos, “Fast Optimization of Nano-CMOS Mixed-Signal Circuits Through Accurate Metamodeling”, in Proceedings of the 12th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 405--410, 2011 (blind review, 92 regular papers and 34 poster papers accepted out of 290 submissions, acceptance rate - 43.4%).
  9. O. Garitselov, S. P. Mohanty, E. Kougianos, and P. Patra, “Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study”, in Proceedings of the 1st IEEE International Symposium on Electronic System Design (ISED), pp. 191--196, 2010 (blind review, 41 papers accepted out of 120 submissions, acceptance rate – 34.1%).
  10. S. P. Mohanty, D. Ghai, and E. Kougianos, “A P4VT (Power-Performance-Process-Parasitic-Voltage-Temperature) Aware Dual-VTh Nano-CMOS VCO”, in Proceedings of the 23rd IEEE International Conference on VLSI Design (VLSID), pp. 99-104, 2010 (blind review, 70 papers accepted out of 320 submissions, acceptance rate - 21.8%).

Project Deliverables


Nonpolynomial Metamodeling Based Mixed-Signal  Optimization using Memetic Algorithm:

Refer the following presentation for details: Mohanty_ISQED2012-Memetic_Talk.pdf

Fast mixed-signal design optimization flow that combines nonpolynomial metamodels and memetic optimization algorithm.

Proposed Nonpolynomial Metamodel Based Design Flow with Neural Networks and Memetic Algorithms.
Memetic_Design_Flow.jpg

Feed-forward dual layer (FFDL) neural newtorks are considered for nonpolynomial metamodeling. FFDL neural-networks are created for each figure-of-merit  (FoM) of the phase-locked loop (PLL) components in which non-linear hidden layer functions are considered each with varying hidden neurons of 1 to 20. Memetic algorithm is considered for optimization over the neural-network metamodels.

Global Search for Memetic Algorithm that invokes local bee-cololoy algorithm for fine tuning.
Memetic_Algorithm.jpg

A 180nm  phase-locked loop (PLL) is considered as a case study circuit. A total of 21 parameters for transistor sizing are considered during optimization. Two different specifications of PLL design completed  using once created metamodels to demonstrate the reusability of the metamodels.

Global Search for Memetic Algorithm that invokes local bee-cololoy algorithm for fine tuning.
Memetic_Results.jpg


Polynomial Metamodeling Based Mixed-Signal  Optimization using Bee-Colony Algorithm:

Refer the following presentation for details: MohantyISED2011Talk_PLL-BC-Optimization.pdf

Fast mixed-signal design optimization flow that combines polynomial metamodels and artificial bee colony (ABC) optimization algorithm.

Proposed Design Flow using Polynomial Metamodels and ABC algorithm.
ABC_Design_Flow.jpg

A 180nm phase-locked loop (PLL) which is the heart of all synchronous circuits and systems is used as a case study circuit.

Case Study Circuit: 180nm PLL Design.
PLL Block Diagram.
ABC_PLL_Block_Diagram.jpg
180nm PLL Layout.
ABC_PLL_Layout.jpg

Polyonomial metamodels of the figures-of-merits (FoMs) of the PLL components are used in the design flow.

Polyonomial Metamodels for PLL Components: Order Versus Coefficients
ABC_Polynomial_Metamodels_Orders.jpg

Artificial bee colony algorithm is used for the optimization over polynomial metamodels. In the algorithm, position of a food source --> a solution; Nectar amount --> Quality of a solution; Number of worker bees --> number of solutions in the population.

Artificial Bee Colony (ABC) Optimization Algorithm: Key Features
ABC_Algorithm.jpg

Experimental Results for 180nm PLL
ABC_Results.jpg


Polynomial Metamodeling Based Mixed-Signal Design Optimization:

The fast and yet accurate single-iteration design flow that combines polynomial metamodels and selected optimization algorithms.
 

Polynomial Metamodel Based Design Flow with Optimization Algorithm over Metamodels.
Matemodel_Based_Design_Flow_Detailed
 

Three Optimization Algorithms: Exhaustive, Tabu-Search and Simulated-Annealing invesitgated,
Results of Simulated Annealing Algorithm Optimization.
RO_45nm_Simulated_Annealing_Optimization_Result_Tables
Results of Tabu Search Algorithm Optimization.
RO_45nm_Tabu_Search_Optimization_Result_Tables
Comparison of Optimization Algorithm Results.
RO_45nm_Optimization_Result_Comparison_Chart

     
Sampling Techniques for Accurate Metamodeling:

Refer the following presentation for details: MohantyISED2010MetamodelingTalk.pdf

The fast and yet accurate single-iteration design flow that combined metamodels and optimization algorithms.
 
Metamodel-Based Design Flow.
Matemodel_Based_Design_Flow

Design of 45nm Ring Oscillator Circuit.

Ring Oscillator: 45nm CMOS Schematic. Ring Oscillator: 45nm CMOS Layout.
RO_45nm_Schematic
RO_45nm_Layout

The sampling techniques applied to the 45nm Ring Oscillator Circuit.
Sampled Space for 5000 Points.
RO_45nm_Sampling_Space

RMSE Comparison for Samping Techniques in MHz.
RO_45nm_Sampling_RMSE_Comparison_Table


Accurate and Single Iteration Design Flow:

Refer the following presentation for details: MohantyICVD2010P4VTtalk.pdf

The accurate design flow for P4VT optimal VCO. This achieves design closure in one manual iteration involving two manual layouts only.

Accurate design flow for P4VT optimal VCO.
P4VT_Optimal_Accurate_Design_Flow.jpg

PVT Variation Analysis of VCO for different FoMs.

Distribution of f0 of a VCO for process-voltage variation at room temperature (27oC). VCO frequency vs. temperature characteristics.
VCO_90nm_Center_Frequency_PDF
VCO_90nm_Center_Frequency_Vs_Temperature

The P4VT optimal VCO Design.
P4VT Optimal Dual-Threshold VCO Circuit. P4VT Optimal Dual-Threshold VCO Layout.
P4VT_Optimal_VCO_90nm_Schematic
P4VT_Optimal_VCO_90nm_Layout





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Last updated on 01 Jan 2013 (Tuesday).
© Saraju P. Mohanty