My research is in Energy-Efficient High-Performance Secure Electronic Systems. The research includes performance modeling of nanoelectronic circuits and systems, incorporation of the models in electronic system design methodologies, and demonstration of the electronic systems for real-life applications. The research can be classified into the following inter-related categories:
Breadth and depth are essential in order to establish a sustainable, active, and high impact research program with strong scholastic output. Depth in research is necessary to explore the underlying fundamental principles and breadth is needed to broaden knowledge and skills so as to remain vigilant and versatile for the ever changing science and technology trends. While individual identity is crucial, interdepartmental, interuniversity, and university-industrial collaborations are essential for high-impact cutting-edge low-power high-performance secure electronic systems research that essentially deals with the fastest growing technologies humankind has known. External funding is very much essential for a high quality, sustainable and productive research program. Funding is used to attract high-quality students and hiring researchers, which is vital for research productivity and output. Various Federal agencies and departments such as the National Science Foundation (NSF), Air Force Research, Department of Energy, and Defense Advanced Research Projects Agency (DARPA) provide funding for research. Moreover, it is of importance to approach various industries for their support and collaboration directly as well as through consortiums, such as the Semiconductor Research Corporation (SRC).
A. Description of Current Research Interests
(1) Methodologies Nanoelectronic Digital and Analog/Mixed-Signal Systems
The objective of this research is to explore models, metamodels, optimization techniques, and design flows for ultra-fast and yet accurate design of digital and analog/mixed-signal (AMS) integrated circuits and systems. A typical consumer electronic system is essentially built as an Analog/Mixed-Signal System-on-a-Chip (AMS-SoC) in which analog and digital portions containing thousands-to-billion nanoelectronic devices are integrated on the same die for cost and performance tradeoffs. Nanoelectronic devices including memristors, graphene transistors, and tunnel transistors have shown significant promise for ultra-low power and very-high speed circuits and systems. To make the situation worse for designers of such high complexity systems the time-to-market has been reduced significantly. In such a situation, design methodology frameworks are more important in order to produce error free AMS-SoCs on time. In this research, new modeling techniques are investigated such that ultra-fast AMS-SoC design exploration can be performed using these models. In particular, techniques for metamodel (model of netlists) generation are investigated. Different types of metamodels are explored for various figures-of-merits (FoMs) of diverse AMS-SoC components. It may be noted that metamodels are not macromodels; the terms "metamodels" and "macromodel" are very distinct even though the two terms are often used in the literature interchangeably. A macromodel is simply a reduced complexity (order) representation of the circuit but is still a netlist, necessitating the use of an analog (SPICE) simulator. The proposed metamodel (which is a mathematical algorithm) is a language and simulator independent model of the original model/netlist (hence the term meta). The simulation time for locking of a phase-locked loop (PLL) over the actual circuit (i.e. full-blown parasitic-aware netlist) is of the order of days to weeks; while the simulation of the PLL over metamodels reduces to minutes! The FoMs of AMS-SoC components for which individual metamodels are generated include power, leakage, frequency, phase-noise, and locking time. In this research, new (metamodeling-based) design methodologies are investigated for AMS-SoC component design optimization. Research also includes integrating the metamodels in the Verilog-AMS and Simscape languages such that AMS-SoC design exploration with layout-level accuracy can be performed. Digital integrated circuits continue to remain the main work horse of AMS-SoC. Hence research also focuses on process-variation aware, power-aware, and security-aware high-level synthesis (HLS) for the realization of efficient register-transfer-level (RTL) description of these digital components. For optimization purposes, various biology and culture inspired algorithms, including bee-colony optimization and memetic algorithms, are investigated as they can handle a large number of parameters and converge rapidly.
(2) Consumer Electronic Systems for Smart Cities
The objective of this research is to explore application specific hardware and software based consumer electronic systems which can be deployed in smart cities. In order to cope up with constrained resources with increased population growth, smart cities with smart technology, smart healthcare, smart grids, smart transportation, smart buildings, and smart communications, are envisioned. The Internet of Things (IoT) which refers to the interconnection of "things" including buildings, energy-grids, transport-systems, and health-care system, which need not be inherently smart, to make them smart through the use of sensors, and information and communication technology (ICT) is the key for building smart cities. IoT frameworks may consist of various diverse components including sensors, electronics, communication networks, middleware, firmware, and software which enable the interactions of many diverse types of things for providing increasingly smart, reliable and secure services. Thus, the realization of IoT systems for smart cities needs the combination of several factors such as energy efficiency, high performance, reliability, security, privacy, and flexibility, which can be drivers of rigorous academic and industrial research. These factors impose significant circuit and system design challenges while keeping the design cost as minimal as possible and meeting the time to market demand. For example, a video processing unit needs to be energy efficient due to the battery source while at the same time needs to have high performance to process high definition video. With the increasing complexity of IoT design, the full-custom, semi-custom, and automatic design methodologies can be explored based on the complexity, time-to-market, and design budgets. At the same time, there is an immediate need for suitable and effective, electronic design automation techniques for the design and implementation of the next generation IoT systems. The research for efficient IoT, may involve circuit and system level challenges targeting specific application domains, e.g. healthcare and, transportation. The IoT system will use various sensors, computing platforms (e.g. smart phones, tablets, personal computers, and servers), middleware, firmware, and software.
(3) VLSI Architectures for Multimedia Signal Processing
The objective of this research is to develop hardware-amenable algorithms and architectures for multimedia data security and copyright protection and to build systems with built-in low-cost, low-power, and real-time digital right management (DRM) facilities following the algorithm-to-board-to-silicon (ABS) developmental approach. For secure, efficient and copyright protected data transmission, there is a need for the following: (a) watermarking techniques for copyright protection of digital video, (b) scrambling techniques for access control, (c) encryption to ensure secured transmission of data, and to also ensure the secure transmission of the scrambling and watermarking keys (if any), and (d) compression techniques to reduce the data transmission rate. Hardware assisted DRM systems that include encryption, watermarking, or scrambling, can be cost effective, real-time, high performance, and power efficient, providing transmission of data with high security and copyright protection. The objective of this research is to introduce hardware amenable algorithms, build secure architectures, and develop complete systems, such as digital cameras, network processors, and graphics processing units, with built-in DRM capabilities. The complete system development will involve FPGA-custom-IC hybrid circuit design, CPU-GPU multi-core, and digital-analog/mixed-signal circuit/system design for low-cost and real-time objectives. Design of low-power high-performance circuits and systems for various applications, like image compression, video compression, biometrics, character recognition, and language translation, are also being considered.
B. Research Significance
The significance of my research is evident from the funded projects, peer-reviewed journal papers, peer-reviewed conference papers, patents, and citations from worldwide peers. The salient features of my research so far are as follows:
C. Research Citations
Last updated on 03 Nov 2015 (Tue).
© Saraju P. Mohanty