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Presentations -- 2006:
  1. Seminar, Indian Institute of Technology (IIT), Kharagpur, India, 27th December 2006 (Secure Digital Camera)
  2. Seminar, Institute of Technical Education and Research (ITER), Bhubaneswar, India, 23rd December 2006 (Design of a Image Watermarking Low-Power Chip)
  3. Seminar, College of Engineering and Technology (CET), Biju Patnaik University of Technology (BPUT), Bhubaneswar, India, 18th December 2006 (Secure Digital Camera)
  4. ICCD 2006 Talk (Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates)
  5. ISQED 2006 Talk (Dual-K Versus Dual-T Technique for Gate Leakage Reduction: A Comparative Perspective)
  6. Seminar, CSCE-5020: Current Research in CSCE, Department of Computer Science and Engineering, University of North Texas, Denton, TX, 15th Feb 2006 (VLSI Design and CAD Research at University of North Texas)
  7. VLSI Design 2006 Talk (A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm)
  8. VLSI Design 2006 Talk (Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits)


Last updated on 01 Jan 2013 (Tuesday).
Saraju P. Mohanty