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Presentations -- 2010:
  1. ISED 2010 Talk (VLSI Design Through Open-Source / Free Tools)
  2. ISED 2010 Talk (Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study)
  3. ISED 2010 Talk (Design of a Reconfigurable Embedded Data Cache)
  4. Seminar, Department of Electrical and Computer Engineering, University of Calgary, Canada, 25th May 2010 (Towards The Design of Robust Secure Digital Cameras (SDC))
  5. GLSVLSI 2010 Talk (A DOE-ILP Assisted Conjugate-Gradient Approach for Power and Stability Optimization in High-κ/Metal-Gate SRAM)
  6. GLSVLSI 2010 Talk (Low Power Nanoscale Buffer Management for Network on Chip Routers)
  7. ISQED 2010 Talk (Layout-Aware Illinois Scan Design for High Fault Coverage)
  8. ISQED 2010 Presentation (On the Design of Different Concurrent EDC Schemes for S-box and GF(P))
  9. ISQED 2010 Presentation (P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP)
  10. ISQED 2010 Talk (A 2-Port 6T SRAM Bitcell Design with Multi-Port Capabilities at Reduced Area Overhead)
  11. VLSI Design 2010 Talk (P4VT (Power-Performance-Process-Parasitic-Voltage-Temperature) Aware Dual-VTh Nano-CMOS VCO)
  12. VLSI Design 2010 Talk (A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM)

Last updated on 01 Jan 2013 (Tuesday).
© Saraju P. Mohanty