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Refereed Publications -- 2003:
  1. S. P. Mohanty, N. Ranganathan, and S. K. Chappidi, "Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling", in Proceedings of the 21st IEEE International Conference on Computer Design (ICCD), pp. 441-443, 2003 (blind review, 61 full papers and 17 short papers accepted out of 233 submissions, acceptance rate - 33.4%).
  2. S. P. Mohanty and N. Ranganathan, "A Framework for Energy and Transient Power Reduction during Behavioral Synthesis", in Proceedings of the 16th International Conference on VLSI Design (VLSID), pp.539-545, 2003 (blind review, 84 accepted out of 210 submissions, acceptance rate - 40%) (Nominated for best paper award; ranked within top 5 papers out of 210 submissions).
  3. S. P. Mohanty and N. Ranganathan, "Energy Efficient Scheduling for Datapath Synthesis", in Proceedings of the 16th International Conference on VLSI Design (VLSID), pp.446-451, 2003 (blind review, 84 accepted out of 210 submissions, acceptance rate - 40%).
  4. S. P. Mohanty, N. Ranganathan, and S. K. Chappidi, "Simultaneous Peak and Average Power Minimization during Datapath Scheduling for DSP Processors", in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.215-220, 2003 (blind review, 17 full papers accepted out of 136 submissions, acceptance rate - 12.5%).
  5. S. P. Mohanty, N. Ranganathan, and S. K. Chappidi, "An ILP-Based Scheduling Scheme for Energy Efficient High Performance Datapath Synthesis", in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 313-316 , 2003.
  6. S. P. Mohanty, N. Ranganathan, and S. K. Chappidi, "Transient Power Minimization Through Datapath Scheduling in Multiple Supply Voltage Environment", in Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Vol. 1, pp. 300-303, 2003.
  7. S. P. Mohanty, N. Ranganathan, and S. K. Chappidi, "Peak Power Minimization through Datapath Scheduling", in Proceedings of the IEEE CS Annual Symposium on VLSI (ISVLSI), pp.121-126, 2003 (26 full papers accepted out of 115 submissions, acceptance rate - 22.6%).
  8. S. P. Mohanty, N. Ranganathan, and R. K. Namballa, "VLSI Implementation of Invisible Digital Watermarking Algorithms Towards the Development of a Secure JPEG Encoder", in Proceedings of the IEEE Workshop on Signal Processing System (SIPS), pp. 183-188, 2003 (67 papers accepted out of 118 submissions, acceptance rate - 56.7%).

Last updated on 01 Jan 2013 (Tuesday).
Saraju P. Mohanty