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Refereed Publications -- 2009:
  1. D. Ghai, S. P. Mohanty, and E. Kougianos, Design of Parasitic and Process Variation Aware RF Circuits: A Nano-CMOS VCO Case Study, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 17, No. 9, September 2009, pp. 1339-1342.
  2. E. Kougianos and S. P. Mohanty, Impact of Gate-Oxide Tunneling on Mixed-Signal Design and Simulation of a Nano-CMOS VCO, Elsevier Microelectronics Journal (MEJ), Volume 40, Issue 1, January 2009, pp. 95-103.
  3. S. P. Mohanty, A Secure Digital Camera Architecture for Integrated Real-Time Digital Rights Management, Elsevier Journal of Systems Architecture (JSA), Volume 55, Issues 10-12, October-December 2009, pp. 468-480.
  4. E. Kougianos and S. P. Mohanty, "Discretization Techniques for the Efficient Solution of the Eigenvalue Problem in Heterostructures", Wiley International Journal of Numerical Modelling: Electronic Networks, Devices and Fields (IJNM), Volume 22, Issue 1, January/ February 2009, pp. 1-21.
  5. E. Kougianos, S. P. Mohanty, and R. N. Mahapatra, "Hardware Assisted Watermarking for Multimedia", Special Issue on Circuits and Systems for Real-Time Security and Copyright Protection of Multimedia, Elsevier International Journal on Computers and Electrical Engineering (IJCEE), Volume 35, Issue 2, March, 2009, pp. 339-358.
  6. J. Singh, D. K. Pradhan, S. Hollis, S. P. Mohanty, and J. Mathew, Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems, in Proceedings of the 12th IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 917-922, 2009 (blind review, 226 papers accepted out of 965 submissions, acceptance rate - 23.4%).
  7. J. Singh, J. Mathew, S. P. Mohanty, and D. K. Pradhan, Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems, in Proceedings of the 22nd International Conference on VLSI Design (VLSID), pp. 307-312, 2009 (blind review, 57 regular papers and 22 short papers accepted out of 320 submissions, acceptance rate - 24.6%).
  8. S. P. Mohanty, D. Ghai, E. Kougianos, and B. Joshi, A Universal Level Converter Towards the Realization of Energy Efficient Implantable Drug Delivery Nano-Electro-Mechanical-Systems, in Proceedings of the 10th International Symposium on Quality Electronic Design (ISQED), pp. 673-679, 2009 (blind review, 87 regular papers accepted out of 300 submissions, acceptance rate - 29%).
  9. D. Ghai, S. P. Mohanty, E. Kougianos, and P. Patra, A PVT Aware Accurate Statistical Logic Library for High-K Metal-Gate Nano-CMOS, in Proceedings of the 10th International Symposium on Quality Electronic Design (ISQED), pp. 47-54, 2009 (blind review, 87 regular papers accepted out of 300 submissions, acceptance rate - 29%).
  10. D. Ghai, S. P. Mohanty, and E. Kougianos, Unified P4 (Power-Performance-Process-Parasitic) Fast Optimization of a Nano-CMOS VCO, in Proceedings of the 19th ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 303-308, 2009 (blind review, 34 full papers and 28 short papers accepted out of 215 submissions, acceptance rate 29%).
  11. D. Ghai, S. P. Mohanty, and E. Kougianos, Variability-Aware Optimization of Nano-CMOS Active Pixel Sensors using Design and Analysis of Monte Carlo Experiments, in Proceedings of the 10th International Symposium on Quality Electronic Design (ISQED), pp. 172-178, 2009 (blind review, 87 regular papers and 50 poster papers accepted out of 300 submissions, acceptance rate 45.7%).
  12. S. P. Mohanty, E. Kougianos, Wei Cai, and M. Ratnani, VLSI Architectures of Perceptual Based Video Watermarking for Real-Time Copyright Protection, in Proceedings of the 10th International Symposium on Quality Electronic Design (ISQED), pp. 527-534, 2009 (blind review, 87 regular papers and 50 poster papers accepted out of 300 submissions, acceptance rate 45.7%).
  13. S. P. Mohanty, GPU-CPU Multi-Core For Real-Time Signal Processing, in Proceedings of the 27th IEEE International Conference on Consumer Electronics (ICCE), pp. 55-56, 2009.
  14. S. P. Mohanty, D. Ghai, E. Kougianos, and P. Patra, A Combined Packet Classifier and Scheduler Towards Net-Centric Multimedia Processor Design, in Proceedings of the 27th IEEE International Conference on Consumer Electronics (ICCE), pp. 11-12, 2009.
  15. S. P. Mohanty and D. K. Pradhan, Tabu Search Based Gate Leakage Optimization using DKCMOS Library in Architecture Synthesis, in Proceedings of the 12th International Conference on Information Technology (ICIT), pp. 3-9, 2009 (blind review, 54 papers accepted out of 148 submissions, acceptance rate 36.4%).
  16. S. P. Mohanty and B. K. Panigrahi, ILP Based Leakage Optimization During Nano-CMOS RTL Synthesis: A DOXCMOS Versus DTCMOS Perspective, in Proceedings of the International Symposium on Biologically Inspired Computing And Applications (BICA), pp. 1367-1372, 2009 (70 papers accepted out of 130 submissions, acceptance rate 53.8%).
  17. E. Kougianos, S. P. Mohanty, and D. K. Pradhan, Simulink Based Architecture Prototyping of Compressed Domain MPEG-4 Watermarking, in Proceedings of the 12th International Conference on Information Technology (ICIT), pp. 10-16, 2009 (blind review, 54 papers accepted out of 148 submissions, acceptance rate 36.4%).

Last updated on 01 Jan 2013 (Tuesday).
Saraju P. Mohanty