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Refereed Publications -- 2011:
  1. S. Banerjee, J. Mathew, D. K. Pradhan, B. B. Bhattacharya, and S. P. Mohanty, "A Routing-Aware ILS Design Technique", IEEE Transaction on VLSI Systems (TVLSI), Vol. 19, No. 12, December 2011, pp. 2335--2338.
  2. S. P. Mohanty and E. Kougianos, Real-Time Perceptual Watermarking Architectures for Video Broadcasting, Elsevier Journal of Systems and Software (JSS), Vol. 84, No. 5, May 2011, pp. 724--738.
  3. S. Banerjee, J. Mathew, S. P. Mohanty, D. K. Pradhan, and M. J. Ciesielski, "A Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization", Special Issue on VLSI Design 2011, ASP Journal of Low Power Electronics (JOLPE), Vol. 7, No. 4, December 2011, pp. 471--481.
  4. U. Choppali, E. Kougianos, S. P. Mohanty, and B. Gorman, Maskless Deposition of ZnO Films, Elsevier Solar Energy Materials and Solar Cells (SOLMAT) Journal, Vol. 95, No. 3, March 2011, pp. 870--876.
  5. S. Banerjee, J. Mathew, D. K. Pradhan, S. P. Mohanty, and M. Ciesielski, Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization, in Proceedings of the 24th International Conference on VLSI Design (VLSID), pp. 304--309, 2011 (blind review, 66 papers accepted out of 330 submissions, acceptance rate -- 20.0%).
  6. O. Okobiah, S. P. Mohanty, E. Kougianos, and M. Poolakkaparambil, Towards Robust Nano-CMOS Sense Amplifier Design: A Dual-Threshold versus Dual-Oxide Perspective, in Proceedings of the 21st ACM Great Lakes Symposium on VLSI (GLSVLSI), 145--150, 2011 (blind review, 57 papers accepted out of 207 submissions, acceptance rate - 27.5%).
  7. S. P. Mohanty and E. Kougianos, PVT-Tolerant 7-Transistor SRAM Optimization via Polynomial Regression, in Proceedings of the 2nd International Symposium on Electronic System Design (ISED), pp. 39--44, 2011 (blind review, 62 papers accepted out of 146 submissions, acceptance rate 42.4%).
  8. O. Garitselov, S. P. Mohanty, E. Kougianos, and P. Patra, Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL, in Proceedings of the 2nd International Symposium on Electronic System Design (ISED), pp. 6--11, 2011 (blind review, 62 papers accepted out of 146 submissions, acceptance rate 42.4%).
  9. M. Poolakkaparambil, J. Mathew, A. Jabir, D. K. Pradhan, and S. P. Mohanty, BCH Code Based Multiple Bit Error Correction in Finite Field Multiplier Circuits, in Proceedings of the 12th International Symposium on Quality Electronic Design (ISQED), pp. 615--620, 2011 (blind review, 92 regular papers accepted out of 290 submissions, acceptance rate - 31.7%).
  10. O. Garitselov, S. P. Mohanty, and E. Kougianos, Fast Optimization of Nano-CMOS Mixed-Signal Circuits Through Accurate Metamodeling, in Proceedings of the 12th International Symposium on Quality Electronic Design (ISQED), pp. 405--410, 2011 (blind review, 92 regular papers and 34 poster papers accepted out of 290 submissions, acceptance rate - 43.4%).
  11. L. Sun, J. Mathew, D. K. Pradhan, and S. P. Mohanty, Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits, in Proceedings of the 2nd International Symposium on Electronic System Design (ISED), pp. 194--199, 2011 (blind review, 62 papers accepted out of 146 submissions, acceptance rate 42.4%).
  12. M. Hosseinabady, P. Lotfi-Kamran, J. Mathew, S. P. Mohanty, and D. K. Pradhan, Single-Event Transient Analysis in High Speed Circuits, in Proceedings of the 2nd International Symposium on Electronic System Design (ISED), pp. 112--117, 2011 (blind review, 62 papers accepted out of 146 submissions, acceptance rate 42.4%).

Last updated on 01 Jan 2013 (Tuesday).
© Saraju P. Mohanty