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Refereed Publications -- 2017:
  1. C. Yang, D. Puthal, S. P. Mohanty, and E. Kougianos, “Big-Sensing-Data Curation for the Cloud is Coming”, IEEE Consumer Electronics Magazine (CEM), Volume 7, Issue 4, October 2017, pp. 48--56.
  2. D. Puthal, S. P. Mohanty, P. Nanda, and U. Choppali, “Building Security Perimeters to Protect Network Systems Against Cyber Threats”, IEEE Consumer Electronics Magazine (CEM), Volume 7, Issue 4, October 2017, pp. 24--27.
  3. S. P. Mohanty, A. Sengupta, P. Guturu, and E. Kougianos, "Everything You Want to Know About Watermarking", IEEE Consumer Electronics Magazine (CEM), Volume 7, Issue 3, July 2017, pp. 83--91.
  4. A. Majumder, J. Goswami, S. Ghosh, R. Shrivastawa, S. P. Mohanty, and B. K. Bhattacharyya, "Pay-Cloak: A Biometric Back Cover for Smartphone with Tokenization Principle for Cashless Payment", IEEE Consumer Electronics Magazine (CEM), Volume 7, Issue 2, April 2017, pp. 78--88.
  5. S. Ghosh, J. Goswami, A. Majumder, A. Kumar, S. P. Mohanty, and B. K. Bhattacharyya, "Swing-Pay: One Card Meets All User Payment and Identity Needs", IEEE Consumer Electronics Magazine (CEM), Volume 7, Issue 1, January 2017, pp. 82--93.
  6. A. Sengupta, D. Roy, and S. P. Mohanty, "Triple-Phase Watermarking for Reusable IP Core Protection during Architecture Synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume X, Issue Y, 2017, pp. Accepted on 13 July 2017.
  7. A. Sengupta, S. Bhadauria, and S. P. Mohanty, “TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling with Optimal Loop Unrolling Factor during High Level Synthesis”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 36, Issue 4, April 2017, pp. 655--668.
  8. M. Sarkar, P. Ghosal, and S. P. Mohanty, "Exploring the Feasibility of a DNA Computer: Design of an ALU using Sticker Based DNA Model", IEEE Transactions on NanoBioscience (TNB), Volume 16, Issue 6, September 2017, pp. 383-399.
  9. V. P. Yanambaka, S. P. Mohanty, E. Kougianos, D. Ghai, and G. Ghai, "Process Variation Analysis and Optimization of a FinFET based VCO", IEEE Transactions on Semiconductor Manufacturing (TSM), Volume 30, Issue 02, May 2017, pp. 126-134.
  10. A. Sengupta, S. Bhadauria, and S. P. Mohanty, “Low-Cost Security Aware HLS Methodology”, IET Computers & Digital Techniques (CDT), Volume 11, Issue 2, March 2017, pp. 68--79.
  11. U. Albalawi, S. P. Mohanty, and E. Kougianos, “A New Region Aware Invisible Robust Blind Watermarking Approach”, Springer Multimedia Tools and Applications Journal, Volume 76, Issue 20, October 2017, pp. 21303–21337.
  12. V. P. Yanambaka, S. P. Mohanty, and E. Kougianos, “Making Use of Semiconductor Manufacturing Process Variations: FinFET-based Physical Unclonable Functions for Efficient Security Integration in the IoT”, Springer Analog Integrated Circuits and Signal Processing Journal, Volume XX, Issue YY, ZZ 2017, pp. Accepted on 20 Sep 2017.
  13. Z. Zhao, A. Srivastava, L. Peng, S. Chen, and S. P. Mohanty, “A Novel Switchable Pin Method for Regulating Power in Chip-Multiprocessor”, Special Issue on Hardware Assisted Techniques for IoT and Bigdata Applications, Elsevier The VLSI Integration Journal, Volume 58, June 2017, pp. 329--338.
  14. M. Sarkar, P. Ghosal, and S. P. Mohanty, “Minimal Reversible Circuit Synthesis on a DNA Computer”, Springer Natural Computing Journal, Volume 16, Issue 3, September 2017, pp. 463--472.
  15. V. P. Yanambaka, S. P. Mohanty, E. Kougianos, P. Sundaravadivel, and J. Singh, “Reconfigurable Robust Hybrid Oscillator Arbiter PUF for IoT Security based on DL-FET”, in Proceedings of the 16th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, pp. 665--670.
  16. V. P. Yanambaka, S. P. Mohanty, E. Kougianos, P. Sundaravadivel, and J. Singh, “Dopingless Transistor Based Hybrid Oscillator Arbiter Physical Unclonable Function”, in Proceedings of the 16th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, pp. 609--614.
  17. Z. Zhao, X. Chen, A. Srivastava, L. Peng, and S. P. Mohanty, “Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design”, in Proceedings of the 16th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, pp. 562--567.

Last updated on 22 Sep 2017 (Fri).
© Saraju P. Mohanty