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Publications -- 2006:
  1. S. P. Mohanty, N. Ranganathan, and K. Balakrishnan, "A Dual Voltage-Frequency VLSI Chip for Image Watermarking in DCT Domain", IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 53, No. 5, May 2006, pp. 394-398.
  2. S. P. Mohanty, N. Ranganathan, and S. K. Chappidi, "ILP Models for Simultaneous Energy and Transient Power Minimization during Behavioral Synthesis", ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 1, January 2006, pp. 186-212.
  3. S. P. Mohanty and E. Kougianos, "Biosensors: A Tutorial Review", IEEE Potentials, Vol. 25, No. 2, March/April 2006, pp. 35-40.
  4. W. Li, S. P. Mohanty, and K. Kavi, "A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator", IEEE Computer Architecture Letters, Vol. 5, No. 2, July/December 2006.
  5. E. Kougianos and S. P. Mohanty, "The Effect of Transverse Energy on Electronic Bound States in Heterostructure Quantum Wells", IOP Semiconductor Science and Technology (SST), Vol. 21, No. 10, October 2006, pp. 1472-1477 (2010 Physics Nobel Prize Winner Andre K. Geim had published two articles in this journal in 1994).
  6. S. P. Mohanty, R. Velagapudi, and E. Kougianos, "Physical-Aware Simulated Annealing Optimization of Gate Leakage in Nanoscale Datapath Circuits", in Proceedings of the 9th IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 1191-1196, 2006 (blind review, 233 papers accepted out of 834 submissions, acceptance rate - 27.9%).
  7. S. P. Mohanty and E. Kougianos, "Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates", in Proceedings of the 24th IEEE International Conference on Computer Design (ICCD), pp. 210-215, 2006 (blind review, 72 papers accepted out of 231 submissions, acceptance rate - 31%).
  8. S. P. Mohanty and E. Kougianos, "Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits", in Proceedings of the 19th International Conference on VLSI Design (VLSID), pp. 83-88, 2006 (blind review, 88 regular papers accepted out of 328 submissions, acceptance rate - 26.8%).
  9. S. P. Mohanty, R. Velagapudi, and E. Kougianos, "Dual-K Versus Dual-T Technique for Gate Leakage Reduction: A Comparative Perspective", in Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED), pp. 564-569, 2006 (blind review, 93 regular papers accepted out of 256 submissions, acceptance rate - 36.3%).
  10. O. B. Adamo, S. P. Mohanty, E. Kougianos, and M. Varanasi, "VLSI Architecture for Encryption and Watermarking Units Towards the Making of a Secure Digital Camera", in Proceedings of the IEEE International SOC Conference (SOCC), pp. 141-144, 2006 (blind review, 53 regular papers accepted out of 169 submissions, acceptance rate - 31.3%).
  11. N. M. Kosaraju, M. Varanasi, and S. P. Mohanty, "A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm", in Proceedings of the 19th International Conference on VLSI Design (VLSID), pp. 481-484, 2006 (blind review, 88 regular papers and 48 short papers accepted out of 328 submissions, acceptance rate - 41.5%).
  12. S. P. Mohanty, P. Guturu, E. Kougianos, and N. Pati, "A Novel Invisible Color Image Watermarking Scheme using Image Adaptive Watermark Creation and Robust Insertion-Extraction", in Proceedings of the IEEE International Symposium on Multimedia (ISM), pp. 153-160, 2006 (acceptance rate - 35%).
  13. S. P. Mohanty, E. Kougianos, R. Velagapudi, and V. Mukherjee, "Scheduling and Binding for Low Gate Leakage NanoCMOS Datapath Circuit Synthesis", in Proceedings of the 38th IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5291-5294, 2006 (1439 papers accepted out of 2429 submissions, acceptance rate - 59%).
  14. E. Kougianos and S. P. Mohanty, "Effective Tunneling Capacitance: A New Metric to Quantify Transient Gate Leakage Current", in Proceedings of the 38th IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2937-2940 , 2006 (1439 papers accepted out of 2429 submissions, acceptance rate - 59%).
  15. Y. Zhuo, H. Li, and S. P. Mohanty, "A Congestion Driven Placement Algorithm for FPGA Synthesis", in Proceedings of the 16th IEEE International Conference on Field Programmable Logic and Applications (FPL), pp. 683-686, 2006 (85 full papers and 80 poster papers accepted out of 307 submissions, acceptance rate - 53.7%).
  16. W. Li, S. P. Mohanty, and K. Kavi, "A Hardware Assisted High Performance PHK Memory Manager", in Proceedings of the ISCA 19th International Conference on Parallel and Distributed Computing Systems (PDCS), pp. 229-234, 2006.
  17. V. Mukherjee, S. P. Mohanty, E. Kougianos, R. Allawadhi, and R. Velagapudi, "Gate Leakage Current Analysis in READ/WRITE/IDLE States of a SRAM Cell", in Proceedings of the IEEE Region 5 Technology and Science Conference, pp. 196-200, 2006.
  18. O. B. Adamo, S. P. Mohanty, E. Kougianos, M. Varanasi, and W. Cai, "VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication", in Proceedings of the IEEE Region 5 Technology and Science Conference, pp. 154-158, 2006.
  19. C. A. Kincaid, S. P. Mohanty, A. R. Mikler, E. Kougianos, and B. Parker, "A High Performance ASIC for Cellular Automata (CA) Applications", in Proceedings of the 9th International Conference on Information Technology (ICIT), pp. 289-290, 2006 (blind review, 83 papers accepted out of 231 submissions, acceptance rate - 35.9%).
  20. G. Sarivisetti, E. Kougianos, S. P. Mohanty, A. Palakodety, and A. K. Ale, "Optimization of a 45nm CMOS Voltage Controlled Oscillator using Design of Experiments", in Proceedings of the IEEE Region 5 Technology and Science Conference, pp. 87-90, 2006.

Last updated on 01 Jan 2013 (Tuesday).
© Saraju P. Mohanty