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Refereed Publications -- 2010:
  1. S. P. Mohanty and D. K. Pradhan, ULS: A Dual-Vth/High-κ Nano-CMOS Universal Level Shifter for System-Level Power Management, Special Issue on Design Techniques for Energy Harvesting, ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 6, No. 2, June 2010, pp. 8:1--8:26.
  2. S. K. Mandal, R. N. Mahapatra, P. S. Bhojwani, and S. P. Mohanty, IntellBatt: Toward A Smarter Battery, IEEE Computer, Vol. 43, No. 3, March 2010, pp. 67--71.
  3. G. Thakral, S. P. Mohanty, D. K. Pradhan, and E. Kougianos, "DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM", Special Issue on VLSI Design 2010, ASP Journal of Low Power Electronics (JOLPE), Vol. 6, No. 3, October 2010, pp. 390--400.
  4. D. Ghai, S. P. Mohanty, and E. Kougianos, A Variability Tolerant System-on-Chip Ready Nano-CMOS Analog-to-Digital Converter (ADC), Taylor & Francis International Journal of Electronics (IJE), Vol. 97, No. 4, April 2010, pp. 421--440.
  5. E. Kougianos and S. P. Mohanty, A Comparative Study on Gate Leakage and Performance of High-ĸ Nano-CMOS Logic Gates, Taylor & Francis International Journal of Electronics (IJE)Vol. 97, No. 9, September 2010, pp. 985--1005.
  6. U. Choppali, E. Kougianos, S. P. Mohanty, and B. Gorman, Polymeric Precursor Derived Nanocrystalline ZnO Thin Films using EDTA as Chelating Agent, Elsevier Solar Energy Materials and Solar Cells (SOLMAT)Vol. 94, No. 12, December 2010, pp. 2351-2357.
  7. Y. -T. Pai, L. -T. Lee, S. -J. Ruan, Y. -H. Chen, S. P. Mohanty, and E. Kougianos, Honeycomb Model Based Skin Color Detector for Face Detection, Special Issue on M2VIP 2008, Inderscience International Journal of Computer Applications in Technology (IJCAT)Vol. 39, Nos. 1/2/3, 2010, pp. 93--100.
  8. S. P. Mohanty, D. Ghai, and E. Kougianos, A P4VT (Power-Performance-Process-Parasitic-Voltage-Temperature) Aware Dual-VTh Nano-CMOS VCO, in Proceedings of the 23rd International Conference on VLSI Design (VLSID), pp. 99-104, 2010 (blind review, 70 papers accepted out of 320 submissions, acceptance rate - 21.8%).
  9. G. Thakral, S. P. Mohanty, D. Ghai, and D. K. Pradhan, A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM, in Proceedings of the 23rd International Conference on VLSI Design (VLSID), pp. 45-50, 2010 (blind review, 70 papers accepted out of 320 submissions, acceptance rate - 21.8%).
  10. G. Thakral, S. P. Mohanty, D. Ghai, and D. K. Pradhan, "A DOE-ILP Assisted Conjugate-Gradient Approach for Power and Stability Optimization in High-κ/Metal-Gate SRAM", in Proceedings of the 20th ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 323-328, 2010 (blind review, 30 full papers accepted out of 165 submissions, acceptance rate 18.1%).
  11. S. K. Mandal, R. Denton, S. P. Mohanty, and R. N. Mahapatra, "Low Power Nanoscale Buffer Management for Network on Chip Routers", in Proceedings of the 20th ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 245-250, 2010 (blind review, 30 full papers accepted out of 165 submissions, acceptance rate 18.1%).
  12. J. Singh, D. S. Aswar, S. P. Mohanty, and D. K. Pradhan, "A 2-Port 6T SRAM Bitcell Design with Multi-Port Capabilities at Reduced Area Overhead", in Proceedings of the 11th International Symposium on Quality Electronic Design (ISQED), pp. 131-138, 2010 (blind review, 84 regular papers accepted out of 270 submissions, acceptance rate - 31.1%).
  13. S. Banerjee, J. Mathew, D. K. Pradhan, and S. P. Mohanty, "Layout-Aware Illinois Scan Design for High Fault Coverage", in Proceedings of the 11th International Symposium on Quality Electronic Design (ISQED), pp. 683-688, 2010 (blind review, 84 regular papers accepted out of 270 submissions, acceptance rate - 31.1%).
  14. J. Mathew, S. Banerjee, H. Rahaman, D. K. Pradhan, S. P. Mohanty, and A. M. Jabir, On the Synthesis of Attack Tolerant Cryptographic Hardware, in Proceedings of the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), pp. 286-291, 2010 (41 full papers accepted out of 199 submissions, acceptance rate 20.6%).
  15. O. Garitselov, S. P. Mohanty, E. Kougianos, and P. Patra, Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study, in Proceedings of the 1st International Symposium on Electronic System Design (ISED), pp. 191--196, 2010 (blind review, 41 papers accepted out of 120 submissions, acceptance rate 34.1%).
  16. S. Banerjee, J. Mathew, D. K. Pradhan, S. P. Mohanty, and M. Ciesielski, A Taylor Expansion Diagram Approach for Nano-CMOS RTL Leakage Optimization, in Proceedings of the 1st International Symposium on Electronic System Design (ISED), pp. 71--76, 2010 (blind review, 41 papers accepted out of 120 submissions, acceptance rate 34.1%).
  17. L. Sun, J. Mathew, D. K. Pradhan, and S. P. Mohanty, Algorithms for Rare Event Analysis in Nano-CMOS Circuits Using Statistical Blockade, in Special Session on New Horizons in SoC and ASIC Design, Proceedings of the International SoC Design Conference (ISOCC), pp. 162--165, 2010.
  18. G. Thakral, S. P. Mohanty, D. Ghai, and D. K. Pradhan, "P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP", in Proceedings of the 11th International Symposium on Quality Electronic Design (ISQED), pp. 176-183, 2010 (blind review, 84 regular papers and 40 poster papers accepted out of 270 submissions, acceptance rate - 45.9%).
  19. J. Mathew, H. Rahaman, A. Jabir, S. P. Mohanty, and D. K. Pradhan, "On the Design of Different Concurrent EDC Schemes for S-box and GF(P)", in Proceedings of the 11th International Symposium on Quality Electronic Design (ISQED), pp. 211-218, 2010 (blind review, 84 regular papers and 40 poster papers accepted out of 270 submissions, acceptance rate - 45.9%).
  20. R. R. Bani, S. P. Mohanty, E. Kougianos, and G. Thakral, Design of a Reconfigurable Embedded Data Cache, in Proceedings of the 1st International Symposium on Electronic System Design (ISED), pp. 163--168, 2010 (blind review, 41 papers accepted out of 120 submissions, acceptance rate 34.1%).
  21. J. Mathew, S. Banerjee, M. Poolakkaparambil, S. P. Mohanty, A. Jabir, and D. K. Pradhan, Multiple-Bit Error Detection and Correction in GF Arithmetic Circuits, in Proceedings of the 1st International Symposium on Electronic System Design (ISED), pp. 101--106, 2010 (blind review, 41 papers accepted out of 120 submissions, acceptance rate 34.1%).

Last updated on 01 Jan 2013 (Tuesday).
Saraju P. Mohanty