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Refereed Publications -- 2007:
  1. S. P. Mohanty, E. Kougianos, and N. Ranganathan, "VLSI Architecture and Chip for Combined Invisible Robust and Fragile Watermarking", IET Computers & Digital Techniques (CDT), September 2007, Volume 1, Issue 5, pp. 600-611.
  2. S. P. Mohanty and E. Kougianos, "Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis", in Proceedings of the 20th International Conference on VLSI Design (VLSID), pp. 577-582, 2007 (blind review, 141 papers accepted out of 444 submissions, acceptance rate - 31.7%).
  3. E. Kougianos and S. P. Mohanty, "Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS Vs PMOS Perspective", in Proceedings of the 20th International Conference on VLSI Design (VLSID), pp. 195-200, 2007 (blind review, 141 papers accepted out of 444 submissions, acceptance rate - 31.7%).
  4. S. P. Mohanty, N. Pati, and E. Kougianos, "A Watermarking Co-Processor for New Generation Graphics Processing Units", in Proceedings of the 25th IEEE International Conference on Consumer Electronics (ICCE), pp. 303-304, 2007.
  5. S. P. Mohanty, O. B. Adamo, and E. Kougianos, "VLSI Architecture of an Invisible Watermarking Unit for a Biometric-Based Security System in a Digital Camera", in Proceedings of the 25th IEEE International Conference on Consumer Electronics (ICCE), pp. 485-486, 2007.
  6. S. P. Mohanty, E. Kougianos, and R. N. Mahapatra, "A Comparative Analysis of Gate Leakage and Performance of High-K Nanoscale CMOS Logic Gates", in Proceedings of the 16th ACM/IEEE International Workshop on Logic and Synthesis (IWLS), pp. 31-38, 2007.
  7. S. P. Mohanty, E. Kougianos, D. Ghai, and P. Patra, "Interdependency Study of Process and Design Parameter Scaling for Power Optimization of Nano-CMOS Circuits under Process Variation", in Proceedings of the 16th ACM/IEEE International Workshop on Logic and Synthesis (IWLS), pp. 207-213, 2007.
  8. J. Singh, J. Mathew, S. P. Mohanty, and D. K. Pradhan, "Statistical Analysis of Steady State Leakage Currents in Nano-CMOS Devices", in Proceedings of the 25th IEEE Norchip Conference (NORCHIP), pp. 1-4, 2007.
  9. S. P. Mohanty, S. T. Vadlamudi, and E. Kougianos, "A Universal Voltage Level Converter for Multi-VDD Based Low-Power Nano-CMOS Systems-on-Chips (SoCs)", in Proceedings of the 13th NASA Symposium on VLSI Design, 2007, CD-ROM Electronic Proceedings paper # 2.2 (7 pages).
  10. S. P. Mohanty and E. Kougianos, "Impact of Gate Leakage on Mixed Signal Design and Simulation of Nano-CMOS Circuits", in Proceedings of the 13th NASA Symposium on VLSI Design, 2007, CD-ROM Electronic Proceedings paper # 2.4 (6 pages).
  11. D. Ghai, S. P. Mohanty, and E. Kougianos, "A 45nm Flash Analog to Digital Converter for Low Voltage High Speed System on Chips", in Proceedings of the 13th NASA Symposium on VLSI Design, 2007, CD-ROM Electronic Proceedings paper # 3.1 (10 pages).
  12. S. P. Mohanty, R. Sheth, A. Pinto, and M. Chandy, "CryptMark: A Novel Secure Invisible Watermarking Technique for Color Images", in Proceedings of the 11th IEEE International Symposium on Consumer Electronics (ISCE), 2007, pp. 1-6.

Last updated on 01 Jan 2013 (Tuesday).
Saraju P. Mohanty