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Refereed Publications -- 2013:
  1. S. P. Mohanty, “Memristor: From Basics to Deployment”, IEEE Potentials, Volume 32, No. 3, May/June 2013, pp. 34--39.
  2. O. Okobiah, S. P. Mohanty, and E. Kougianos, "Geostatistical-Inspired Fast Layout Optimization of a Nano-CMOS Thermal Sensor", IET Circuits, Devices & Systems (CDS), Volume 7, No. 5, September 2013, pp. 253--262.
  3. D. Ghai, S. P. Mohanty, and G. Thakral, “Fast Optimization of Nano-CMOS Voltage-Controlled Oscillator using Polynomial Regression and Genetic Algorithm”, Elsevier Microelectronics Journal (MEJ), Volume 44, Issue 8, August 2013, pp. 631--641.
  4. J. Mathew, S. P. Mohanty, S. Banerjee, D. K. Pradhan, and A. M. Jabir, "Attack Tolerant Cryptographic Hardware Design by Combining Galois Field Error Correction and Uniform Switching Activity", Elsevier International Journal on Computers and Electrical Engineering (IJCEE), Volume 39, No. 4, May 2013, pp. 1077--1087.
  5. S. Nimgaonkar, M. Gomathisankaran, and S. P. Mohanty, “TSV: A Novel Energy Efficient Memory Integrity Verification Scheme for Embedded Systems”, Elsevier Journal of Systems Architecture (JSA), Vol. 59, No. 7, August 2013, pp. 400--411.
  6. S. Nimgaonkar, M. Gomathisankaran, and S. P. Mohanty, “MEM-DnP: A Novel Energy Efficient Approach for Memory Integrity Detection and Protection in Embedded Systems”, Springer Circuits, Systems, and Signal Processing Journal (CSSP), Volume 32, Issue 6, December 2013, pp. 2581--2604.
  7. U. Choppali, E. Kougianos, S. P. Mohanty, and B. Gorman, “Influence of Annealing on Polymeric Precursor Derived ZnO Thin Films on Sapphire”, Elsevier Journal of Thin Solid Films (TSF), Vol. 545, pp. 466--470, October 2013.
  8. O. Okobiah, S. P. Mohanty, and E. Kougianos, “Geostatistics Inspired Fast Layout Optimization of Nanoscale CMOS Phase Locked Loop”, in Proceedings of the 14th International Symposium on Quality Electronic Design (ISQED), 2013, pp. 546--551. (blind review)
  9. D. Ghai, S. P. Mohanty, and G. Thakral, “Fast Analog Design Optimization using Regression based Modeling and Genetic Algorithm: A Nano-CMOS VCO Case Study”, in Proceedings of the 14th International Symposium on Quality Electronic Design (ISQED), 2013, pp. 422--427. (blind review)
  10. G. Zheng, S. P. Mohanty, E. Kougianos, and O. Okobiah, “Polynomial Metamodel Integrated Verilog-AMS for Memristor-Based Mixed-Signal System Design”, in Proceedings of the 56th IEEE International Midwest Symposium on Circuits & Systems (MWSCAS), 2013, pp. 916--919.
  11. O. Okobiah, S. P. Mohanty, and E. Kougianos, “Fast Statistical Process Variation Analysis using Universal Kriging Metamodeling: A PLL Example”, in Proceedings of the 56th IEEE International Midwest Symposium on Circuits & Systems (MWSCAS), 2013, pp. 277--280.
  12. G. Zheng, S. P. Mohanty, E. Kougianos, and O. Okobiah, “iVAMS: Intelligent Metamodel-Integrated Verilog-AMS for Circuit-Accurate System-Level Mixed-Signal Design Exploration”, in Proceedings of the 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2013, pp. 75--78. (24 full, 15 short, and 22 poster papers accepted out of 125 submissions, acceptance rate -- 48.8%)
  13. D. Ghai, S. P. Mohanty, and G. Thakral, “Comparative Analysis of Double Gate FinFET Configurations for Analog Circuit Design”, in Proceedings of the 56th IEEE International Midwest Symposium on Circuits & Systems (MWSCAS), 2013, pp. 809--812.
  14. D. Ghai, S. P. Mohanty, and G. Thakral, “Double Gate FinFET based Mixed-Signal Design: A VCO Case Study”, in Proceedings of the 56th IEEE International Midwest Symposium on Circuits & Systems (MWSCAS), 2013, pp. 177--180.
  15. M. Sarkar, P. Ghosal, and S. P. Mohanty, “Reversible Circuit Synthesis Using ACO and SA based Quinne-McCluskey Method”, in Proceedings of the 56th IEEE International Midwest Symposium on Circuits & Systems (MWSCAS), 2013, pp. 416--419.

Last updated on 03 Nov 2013 (Sun).
© Saraju P. Mohanty